LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

文件：140.5 Kbytes 页数：11 Pages

IDT

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

文件：140.5 Kbytes 页数：11 Pages

IDT

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

文件：140.5 Kbytes 页数：11 Pages

IDT

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

文件：140.5 Kbytes 页数：11 Pages

IDT

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

文件：140.5 Kbytes 页数：11 Pages

IDT

LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting

文件：140.5 Kbytes 页数：11 Pages

IDT