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IDT72T4098L10BBI中文资料IDT数据手册PDF规格书
IDT72T4098L10BBI规格书详情
DESCRIPTION
The IDT72T4088/72T4098/72T40108/72T40118 are exceptionally deep, extremely high speed, CMOS First-In-First-Out (FIFO) memories with the ability to read and write data on both rising and falling edges of clock. The device has a flexible x40/x20/x10 Bus-Matching mode and the option to select single or double data rates for input and output ports. These FIFOs offer several key user benefits:
• Flexible x40/x20/x10 Bus-Matching on both read and write ports
• Ability to read and write on both rising and falling edges of a clock
• User selectable Single or Double Data Rate of input and output ports
• A user selectable MARK location for retransmit
• User selectable I/O structure for HSTL or LVTTL
• The first word data latency period, from the time the first word is written to an empty FIFO to the time it can be read, is fixed and short.
• High density offerings up to 5Mbit
• 10Gbps throughput
FEATURES
• Choose among the following memory organizations:
IDT72T4088 ― 16,384 x 40
IDT72T4098 ― 32,768 x 40
IDT72T40108 ― 65,536 x 40
IDT72T40118 ― 131,072 x 40
• Up to 250MHz operating frequency or 10Gbps throughput in SDR mode
• Up to 110MHz operating frequency or 10Gbps throughput in DDR mode
• Users selectable input port to output port data rates, 500Mb/s Data Rate
-DDR to DDR
-DDR to SDR
-SDR to DDR
-SDR to SDR
• User selectable HSTL or LVTTL I/Os
• Read Enable & Read Clock Echo outputs aid high speed operation
• 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage
• 3.3V Input tolerant
• Mark & Retransmit, resets read pointer to user marked position
• Write Chip Select (WCS) input enables/disables Write Operations
• Read Chip Select (RCS) synchronous to RCLK
• Programmable Almost-Empty and Almost-Full flags, each flag can default to one of four preselected offsets
• Dedicated serial clock input for serial programming of flag offsets
• User selectable input and output port bus sizing
-x40 in to x40 out
-x40 in to x20 out
-x40 in to x10 out
-x20 in to x40 out
-x10 in to x40 out
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable settings
• Empty and Full flags signal FIFO status
• Select IDT Standard timing (using EF and FF flags) or First Word Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into High-Impedance state
• JTAG port, provided for Boundary Scan function
• 208 Ball Grid array (PBGA), 17mm x 17mm, 1mm pitch
• Easily expandable in depth and width
• Independent Read and Write Clocks (permit reading and writing simultaneously)
• High-performance submicron CMOS technology
• Industrial temperature range (-40°C to +85°C) is available
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
IDT |
23+ |
208PBGA |
9000 |
原装正品,支持实单 |
询价 | ||
IDT |
23+ |
256BGA |
9526 |
询价 | |||
IDT |
22+ |
208PBGA |
9000 |
原厂渠道,现货配单 |
询价 | ||
IDT, Integrated Device Techno |
23+ |
208-PBGA17x17 |
7300 |
专注配单,只做原装进口现货 |
询价 | ||
IDT, Integrated Device Techno |
23+ |
208-PBGA17x17 |
7300 |
专注配单,只做原装进口现货 |
询价 | ||
IDT |
2022+ |
原厂原包装 |
38550 |
全新原装 支持表配单 中国著名电子元器件独立分销 |
询价 | ||
IDT |
21+ |
208PBGA |
13880 |
公司只售原装,支持实单 |
询价 | ||
IDT, Integrated Device Technol |
21+ |
208-PBGA(17x17) |
53200 |
一级代理/放心采购 |
询价 | ||
IDT |
23+ |
NA |
19960 |
只做进口原装,终端工厂免费送样 |
询价 | ||
IDT |
20+ |
BGA-208 |
1001 |
就找我吧!--邀您体验愉快问购元件! |
询价 |