Fully integrated PLL

文件：167 Kbytes 页数：16 Pages

IDT

Low Skew, 1-to-15, LVCMOS/LVTTL Clock Generator

文件：245.2 Kbytes 页数：16 Pages

IDT

Low Skew, 1-to-15, LVCMOS/LVTTL Clock Generator

FEATURES • Fully integrated PLL • Fifteen single ended 3.3V LVCMOS/LVTTL outputs • Two LVCMOS/LVTTL clock inputs for redundant clock applications • CLK0 and CLK1 accepts the following input levels: LVCMOS/LVTTL • Output frequency range: 8.33MHz to 125MHz • VCO range: 200MHz to 500MHz • Ext

文件：440.14 Kbytes 页数：17 Pages

RENESAS

瑞萨

Low Skew, 1-to-15, LVCMOS/LVTTL Clock Generator

文件：245.2 Kbytes 页数：16 Pages

IDT