1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR

GENERAL DESCRIPTION The ICS87004 is a highly versatile 1:4 Differentialto-LVCMOS/LVTTL Clock Generator and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS87004 has two selectable clock inputs. The CLK0, nCLK0 and CLK1, nCLK1 pairs can accept most standard

文件：185.16 Kbytes 页数：14 Pages

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丝印：ICS87004AG；Package：TSSOP；1:4, Differential-to-LVCMOS/LVT

Features • Four LVCMOS/LVTTL outputs, 7Ω typical output impedance • Selectable CLK0/nCLK0 or CLK1/nCLK1 clock inputs • CLKx/nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Internal bias on nCLK0 and nCLK1 to support LVCMOS/LVTTL levels on CL

文件：829.71 Kbytes 页数：16 Pages

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丝印：ICS87004AG；Package：TSSOP；1:4, Differential-to-LVCMOS/LVT

Features • Four LVCMOS/LVTTL outputs, 7Ω typical output impedance • Selectable CLK0/nCLK0 or CLK1/nCLK1 clock inputs • CLKx/nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Internal bias on nCLK0 and nCLK1 to support LVCMOS/LVTTL levels on CL

文件：829.71 Kbytes 页数：16 Pages

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瑞萨

1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR

GENERAL DESCRIPTION The ICS87004 is a highly versatile 1:4 Differentialto-LVCMOS/LVTTL Clock Generator and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS87004 has two selectable clock inputs. The CLK0, nCLK0 and CLK1, nCLK1 pairs can accept most standard

文件：185.16 Kbytes 页数：14 Pages

ICST

1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR

Renesas

瑞萨

丝印：ICS87004AGLF；Package：TSSOP；1:4, Differential-to-LVCMOS/LVT

Features • Four LVCMOS/LVTTL outputs, 7Ω typical output impedance • Selectable CLK0/nCLK0 or CLK1/nCLK1 clock inputs • CLKx/nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Internal bias on nCLK0 and nCLK1 to support LVCMOS/LVTTL levels on CL

文件：829.71 Kbytes 页数：16 Pages

RENESAS

瑞萨

丝印：ICS87004AGLF；Package：TSSOP；1:4, Differential-to-LVCMOS/LVT

Features • Four LVCMOS/LVTTL outputs, 7Ω typical output impedance • Selectable CLK0/nCLK0 or CLK1/nCLK1 clock inputs • CLKx/nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Internal bias on nCLK0 and nCLK1 to support LVCMOS/LVTTL levels on CL

文件：829.71 Kbytes 页数：16 Pages

RENESAS

瑞萨

1:4/ DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR

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