Low Skew, 1-to-6, Differential-to - LVDS Fanout Buffer One differential clock input pair

文件：205.66 Kbytes 页数：15 Pages

IDT

Low Skew, 1-to-6, Differential-to-LVDS Fanout Buffer

文件：691.85 Kbytes 页数：17 Pages

IDT

Low Skew, 1-to-6, Differential-to-LVDS Fanout Buffer

Features ▪ Six differential LVDS outputs ▪ One differential clock input pair ▪ CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL ▪ Maximum output frequency: 1.7GHz ▪ Translates any single-ended input signal to LVDS levels with resistor bias

文件：1.09572 Mbytes 页数：18 Pages

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Low Skew, 1-to-6, Differential-to- LVDS Fanout Buffer

文件：205.66 Kbytes 页数：15 Pages

IDT