LVPECL Fanout Buffer

GENERAL DESCRIPTION The ICS8535-01 is a low skew, high performance 1-to-4 LVCMOS/LVTTL-to-3.3V LVPECL fanout buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from IDT. The ICS8535-01 has two single ended clock inputs. FEATURES • Four differential 3.3V LVPECL ou

文件：424.32 Kbytes 页数：18 Pages

IDT

Low Skew, 1-to-4 LVCMOS/LVTTL-to-3.3V LVPECL Fanout Buffer

Features •Fourdifferential3.3VLVPECLoutputs •SelectableCLK0orCLK1inputsforredundantandmultiplefrequencyfanoutapplications •CLK0orCLK1canacceptthefollowinginputlevels:LVCMOSorLVTTL •Maximumoutputfrequency:266MHz •TranslatesLVCMOSandLVTTLlevelsto3.3VLVPECLlevels •Outputskew:30ps(maximum) •Par

文件：861.5 Kbytes 页数：19 Pages

RENESAS

瑞萨

LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL FANOUT BUFFER

GENERAL DESCRIPTION The ICS8535-01 is a low skew, high performance 1-to-4 LVCMOS-to-3.3V LVPECL fanout buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8535-01 has two single ended clock inputs. FEATURES • 4 differential 3.3V LVPECL outputs •

文件：115.08 Kbytes 页数：12 Pages

ICST

LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL FANOUT BUFFER

DESCRIPTION: The IDT8535-01 is a low skew, high performance 1-to-4 LVCMOS-to-3.3V LVPECL fanout buffer. It has two single-ended clock inputs. The single-ended clock input accepts LVCMOS or LVTTL input levels and translates them to 3.3V LVPECL levels. The clock enable is internally synchronized to

文件：75.44 Kbytes 页数：11 Pages

IDT

LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL FANOUT BUFFER

DESCRIPTION: The IDT8535-01 is a low skew, high performance 1-to-4 LVCMOS-to-3.3V LVPECL fanout buffer. It has two single-ended clock inputs. The single-ended clock input accepts LVCMOS or LVTTL input levels and translates them to 3.3V LVPECL levels. The clock enable is internally synchronized to

文件：75.44 Kbytes 页数：11 Pages

IDT

LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL FANOUT BUFFER

DESCRIPTION: The IDT8535-01 is a low skew, high performance 1-to-4 LVCMOS-to-3.3V LVPECL fanout buffer. It has two single-ended clock inputs. The single-ended clock input accepts LVCMOS or LVTTL input levels and translates them to 3.3V LVPECL levels. The clock enable is internally synchronized to

文件：75.44 Kbytes 页数：11 Pages

IDT