ICS613MT集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

描述 Description

The ICS613 is a low cost, low phase noise, high performance clock synthesizer for any applications that require low phase noise and low jitter. It is ICS’ lowest phase noise multiplier. Using ICS’ patented analog and digital Phase Locked Loop (PLL) techniques, the chip can accept a 25MHz crystal or clock input, and produces output clocks up to 157.5 MHz.

特性 Features

• Packaged in 16 pin SOIC

• Available in Pb (lead) free package

• Uses a fundamental 25MHz crystal or clock

• Operating voltage of 3.3 V

• Separate output voltage supplies which can run at 2.5 V or 3.3 V

• Output clocks up to 157.5 MHz

• Low phase noise: -110 dBc/Hz at 10 kHz

• Low jitter of 36 ps (one sigma)

• Advanced, low power, sub-micron CMOS process