ICS601R-25集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

Description

The ICS601-25 is a low-cost, low phase noise, high performance clock synthesizer for applications which require low phase noise, low jitter, and low skew fanout. It is ICS’ lowest phase noise multiplier, and also the lowest CMOS part in the industry. Using ICS’ patented analong and digital Phase Locked Loop (PLL) techniques, the chip accepts a 10-27 MHz crystal or clock input, and produces output clocks up to 156 MHz.

Features

• Packaged in 20-pin SSOP

• Uses fundamental 10 - 27 MHz crystal or clock

• Output clocks up to 156 MHz

• Low phase noise: -132 dBc/Hz at 10 kHz

• Five low skew (<250 ps) outputs

• Low jitter - 18 ps one sigma at 125 MHz

• Full swing CMOS outputs with 25 mA drive capability at TTL levels

• Powerdown mode lowers power consumption

• Advanced, low power, sub-micron CMOS process

• Industrial temperature version available

• Available in Pb (lead) free package

• Operating voltage of 3.3 V