ICS601M-01I集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

Description

The ICS601-01 is a low-cost, low phase noise, high-performance clock synthesizer for applications which require low phase noise and low jitter. It is ICS’ lowest phase noise multiplier, and also the lowest CMOS part in the industry. Using ICS’ patented analong and digital Phase-Locked Loop (PLL) techniques, the chip accepts a 10 - 27 MHz crystal or clock input, and produces output clocks up to 156 MHz at 3.3 V.

Features

• Packaged in 16-pin SOIC or TSSOP

• Available in Pb (lead) free package

• Uses fundamental 10 - 27 MHz crystal or clock

• Patented PLL with the lowest phase noise

• Output clocks up to 156 MHz at 3.3 V

• Low phase noise: -132 dBc/Hz at 10 kHz

• Low jitter - 18 ps one sigma typ.

• Full swing CMOS outputs with 25 mA drive capability at TTL levels

• Advanced, low power, sub-micron CMOS process

• Industrial temperature range available

• Operating voltage of 3.3V or 5V