ICS601-21中文资料ICST数据手册PDF规格书

描述 Description

The ICS601-21 is a low-cost, low phase noise, high performance clock synthesizer for applications which require low phase noise and low jitter. It is ICS’ lowest phase noise multiplier. Using ICS’ patented analog and digital Phase Locked Loop (PLL) techniques, the chip accepts a 10 - 27 MHz crystal or clock input, and produces output clocks up to 220 MHz at 3.3 V.

特性 Features

• Fully integrated PLL, no external loop filter required

• Differential 3.3 V LVPECL outputs

• Uses fundamental 10 - 27 MHz crystal or clock

• Output clocks up to 220 MHz at 3.3 V

• Low phase noise: -122 dBc/Hz at 10 kHz

• Low jitter - 15 ps one sigma typ.

• Powerdown mode lowers power consumption

• Packaged in 16-pin TSSOP

• Advanced, low power, sub-micron CMOS process

• Operating voltage of 3.3 V

• Commercial temperature range available