ICS552R-01集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

Description

The ICS552-01A produces 8 low skew copies of a multiple of the input when a clock or fundamental, parallel-mode crystal is connected to it. Unlike other clock drivers, it does not require a separate oscillator for the input. Using a phase locked loop (PLL) to multiply the input frequency, it is ideal for generating and distributing multiple high frequency clocks.

Features

• Packaged in 20 pin SSOP (QSOP)

• Input frequency of 10.0 - 27.0 MHz

• Contains on-chip multiplier with selections

of x1, x1.33, x2, x2.66, x3, x3.33, x4, x4.66, x5, and x6

• Provides 8 low skew outputs (<250 ps)

• Output clock duty cycle of 40/60 at 3.3 V

• Operating voltages of 3.0 V to 5.5 V

• Industrial temperature available

• Power Down and Tri state modes