ICS541中文资料PLL Clock Divider数据手册Renesas规格书

描述 Description

The ICS541 is a cost effective way to produce a high quality clock output divided from a clock input. The chip accepts a clock input up to 135 MHz at 3.3 V, and by using proprietary Phase Locked Loop (PLL) techniques, produces a divide by 1, 2, 4, or 8 of the input clock. There are two outputs on the chip, one being a low-skew divide by two of the other. So, for instance, if an 80 MHz input clock is used, the ICS541 can produce low skew 80 MHz and 40 MHz clocks, or 40 MHz and 20 MHz clocks, or 20 MHz and 10MHz clocks. The chip has an all-chip power down mode that stops the outputs low, and an OE pin that tristates the outputs.
The ICS541 is a member of the ICS ClockBlocks™ family of clock building blocks. See the ICS542 and ICS543 for other clock dividers, and the ICS300, 501, 502, and 503 for clock multipliers. Description

特性 Features

• Packaged in 8 pin SOIC
• Low cost clock divider
• Low skew (500ps) outputs. One is ÷ 2 of other.
• Easy to use with other generators and buffers
• Input clock frequency up to 135 MHz at 3.3 V
• Input clock frequency up to 156 MHz at 5.0 V
• Tolerant of poor input clock duty cycle, jitter.
• Output clock duty cycle of 45/55
• Power Down turns off chip
• Output Enable
• Full CMOS clock swings with 25mA drive capability at TTL levels
• Advanced, low power CMOS process
• Operating voltages of 3.0 to 5.5 V