ICS527-04中文资料瑞萨数据手册PDF规格书

特性 Features

• Packaged as 28-pin SSOP (150 mil body)

• Synchronizes fractional clocks rising edges

• CMOS in to PECL out

• PECL in to PECL out

• Pin selectable dividers

• Zero input to output skew

• User determines the output frequency - no software

needed

• Slices frequency or period

• Input clock frequency of 1.5 MHz - 200 MHz

• Output clock frequencies up to 160 MHz

• Very low jitter

• Duty cycle of 45/55

• Operating voltage of 3.3 V

• Advanced, low power CMOS process