ICS2509C中文资料ICST数据手册PDF规格书

General Description

The ICS2509C is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the CLKIN signal with the CLKOUT signal. It is specifically designed for use with synchronous SDRAMs. The ICS2509C operates at 3.3V VCC and drives up to nine clock loads.

特性 Features

• Meets or exceeds PC133 registered DIMM specification 1.1

• Spread Spectrum Clock Compatible

• Distributes one clock input to one bank of five and one bank of four outputs

• Separate output enable(OEA,OEB) for each output bank

• Operating frequency 25 MHz to 175 Mhz

• External feedback input (FBIN) terminal is used to synchrionize the outputs to the clock input

• No external RC network required

• Operates at 3.3V Vcc

• Plastic 24-pin 173mil TSSOP package