丝印：1524AMLF；Package：SIOC-24；Dual Output Phase Controlled SSTL_3/PECL Clock Generator

Features • Wide input frequency range • 8 kHz to 100 MHz • 250 MHz balanced PECL differential outputs • 150 MHz single-ended SSTL_3 clock outputs • Dynamic Phase Adjust (DPA) for DPACLK outputs • Software controlled phase adjustment • 360o Adjustment down to 1/64 clock increments • Externa

文件：786 Kbytes 页数：25 Pages

RENESAS

瑞萨

丝印：1524AMLF；Package：SIOC-24；Dual Output Phase Controlled SSTL_3/PECL Clock Generator

Features • Wide input frequency range • 8 kHz to 100 MHz • 250 MHz balanced PECL differential outputs • 150 MHz single-ended SSTL_3 clock outputs • Dynamic Phase Adjust (DPA) for DPACLK outputs • Software controlled phase adjustment • 360o Adjustment down to 1/64 clock increments • Externa

文件：786 Kbytes 页数：25 Pages

RENESAS

瑞萨

Package：24-SOIC（0.295"，7.50mm 宽）；包装：管件 类别：集成电路（IC） 时钟发生器，PLL，频率合成器 描述：IC CLK GEN SSTL_3/PECL 24-SOIC

Renesas Electronics America Inc

Package：24-SOIC（0.295"，7.50mm 宽）；包装：管件 类别：集成电路（IC） 时钟发生器，PLL，频率合成器 描述：IC CLK GEN SSTL_3/PECL 24-SOIC

Renesas Electronics America Inc