ICS1524AMLF集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

特性 Features

• Wide input frequency range

• 8 kHz to 100 MHz

• 250 MHz balanced PECL differential outputs

• 150 MHz single-ended SSTL_3 clock outputs

• Dynamic Phase Adjust (DPA) for DPACLK outputs

• Software controlled phase adjustment

• 360o Adjustment down to 1/64 clock increments

• External or internal loop filter selection

• Uses 3.3 VDC Inputs are 5 volt tolerant.

• I2C-bus serial interface runs at either low speed

(100 kHz) or high speed (400 kHz).

• Hardware and Software PLL Lock detection