IC61SF12832中文资料128K x 32 Flow Through SyncBurst SRAM数据手册ISSI规格书

描述 Description

DESCRIPTION
The ICSI IC61SF12832 and IC61SF12836 are high-speed synchronous static RAM designed to provide a burstable, high performance for high speed networking and communication applications. It is organized as 131,072 words by 32 bits or 36 bits, fabricated with ICSIs advanced CMOS technology. The device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written. BW1 controls DQa, BW2 controls DQb, BW3 controls DQc, BW4 controls DQd, conditioned by BWE being LOW. A LOW on GW input would cause all bytes to be written.
Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally by the IC61SF12832 and controlled by the ADV (burst address advance) input pin.
The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating.FEATURES
• Fast access times: 7.5 ns, 8 ns, 8.5 ns, 10 ns,
   and 12 ns
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data
   inputs and control signals
• PentiumTM or linear burst sequence control
   using MODE input
• Three chip enables for simple depth expansion
   and address pipelining
• Common data inputs and data outputs
• 100-Pin TQFP (JEDEC LQFP) and
   119-pin PBGA package
• Single +3.3V +10%, -5% power supply
• Power-down snooze mode

特性 Features

• Fast access times: 7.5 ns, 8 ns, 8.5 ns, 10 ns,
   and 12 ns
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data
   inputs and control signals
• PentiumTM or linear burst sequence control
   using MODE input
• Three chip enables for simple depth expansion
   and address pipelining
• Common data inputs and data outputs
• 100-Pin TQFP (JEDEC LQFP) and
   119-pin PBGA package
• Single +3.3V +10%, -5% power supply
• Power-down snooze mode