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HY5DV641622AT-5中文资料PDF规格书
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DESCRIPTION
The Hynix HY5DV641622 is a 67,108,864-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the point-to-point applications which requires high bandwidth.
FEATURES
•3.3V for VDDand 2.5V for VDDQpower supply
• All inputs and outputs are compatible with SSTL_2 interface
• JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous - data transaction aligned to bidirectional data strobe (DQS)
• x16 device has 2 bytewide data strobes (LDQS, UDQS) per each x8 I/O
• Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ)
• Data(DQ) and Write masks(DM) latched on the both rising and falling edges of the data strobe
• All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock
• Write mask byte controls by LDM and UDM
• Programmable /CAS Latency 3 / 4 supported
• Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode
• Internal 4 bank operations with single pulsed /RAS
• tRAS Lock-Out function supported
• Auto refresh and self refresh supported
• 4096 refresh cycles / 64ms
• Full, Half and Matched Impedance(Weak) strength driver option controlled by EMRS
产品属性
- 型号:
HY5DV641622AT-5
- 制造商:
SK Hynix Inc
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
HYUNDAI |
1926+ |
TSOP |
6852 |
只做原装正品现货!或订货假一赔十! |
询价 | ||
HYNIX |
SMDRefubt |
8560 |
一级代理 原装正品假一罚十价格优势长期供货 |
询价 | |||
HYNIX |
9308 |
322 |
原装正品长期供货,如假包赔包换 徐小姐13714450367 |
询价 | |||
HY |
23+ |
NA |
107 |
航宇科工半导体-中国航天科工集团战略合作伙伴! |
询价 | ||
HYNIX |
23+ |
NA/ |
117 |
优势代理渠道,原装正品,可全系列订货开增值税票 |
询价 | ||
HY |
23+ |
TSOP |
96880 |
只做原装,欢迎来电资询 |
询价 | ||
HY |
21+ |
TSOP |
13880 |
公司只售原装,支持实单 |
询价 | ||
HY5DV641622AT-5 |
86 |
86 |
询价 | ||||
HYNIX |
2022 |
TSOP |
80000 |
原装现货,OEM渠道,欢迎咨询 |
询价 | ||
HYNIX |
TSSOP |
10265 |
提供BOM表配单只做原装货值得信赖 |
询价 |