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HY5DV641622AT-33中文资料SK海力士数据手册PDF规格书
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DESCRIPTION
The Hynix HY5DV641622 is a 67,108,864-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the point-to-point applications which requires high bandwidth.
FEATURES
•3.3V for VDDand 2.5V for VDDQpower supply
• All inputs and outputs are compatible with SSTL_2 interface
• JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous - data transaction aligned to bidirectional data strobe (DQS)
• x16 device has 2 bytewide data strobes (LDQS, UDQS) per each x8 I/O
• Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ)
• Data(DQ) and Write masks(DM) latched on the both rising and falling edges of the data strobe
• All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock
• Write mask byte controls by LDM and UDM
• Programmable /CAS Latency 3 / 4 supported
• Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode
• Internal 4 bank operations with single pulsed /RAS
• tRAS Lock-Out function supported
• Auto refresh and self refresh supported
• 4096 refresh cycles / 64ms
• Full, Half and Matched Impedance(Weak) strength driver option controlled by EMRS
产品属性
- 型号:
HY5DV641622AT-33
- 制造商:
HYNIX
- 制造商全称:
Hynix Semiconductor
- 功能描述:
64M(4Mx16) DDR SDRAM
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
SKHYNIX/海力士 |
23+ |
TSSOP |
3956 |
一级代理原厂VIP渠道,专注军工、汽车、医疗、工业、 |
询价 | ||
HYNIX |
19+ |
256800 |
原厂代理渠道,每一颗芯片都可追溯原厂; |
询价 | |||
HYNIX |
22+ |
TSSOP |
4650 |
询价 | |||
HY |
23+ |
TSSOP |
5000 |
专注配单,只做原装进口现货 |
询价 | ||
HYNIX |
23+ |
TSOP |
50000 |
全新原装正品现货,支持订货 |
询价 | ||
海力士 |
2021+ |
TSOP |
100500 |
一级代理专营品牌!原装正品,优势现货,长期排单到货 |
询价 | ||
HY |
1922+ |
TSOP |
9865 |
原装进口现货库存专业工厂研究所配单供货 |
询价 | ||
HY |
22+23+ |
TSOP |
40672 |
绝对原装正品全新进口深圳现货 |
询价 | ||
HY |
24+ |
SOP |
96880 |
只做原装,欢迎来电资询 |
询价 | ||
HY |
02+ |
TSOP |
956 |
询价 |