OCTAL BUFFERS AND LINE DRIVERS

文件：1.341 Mbytes 页数：21 Pages

TI

德州仪器

Low DC Power Consumption

文件：104.2 Kbytes 页数：2 Pages

HW

汉威光电

PRELIMINARY INFORMATION PLL Clock Divider

The ICS541 is a cost effective way to produce a high quality clock output divided from a clock input. The chip accepts a clock input up to 135 MHz at 3.3 V, and by using proprietary Phase Locked Loop (PLL) techniques, produces a divide by 1, 2, 4, or 8 of the input clock. There are two outputs on

文件：59.89 Kbytes 页数：4 Pages

ICST

PRELIMINARY INFORMATION PLL Clock Divider

The ICS541 is a cost effective way to produce a high quality clock output divided from a clock input. The chip accepts a clock input up to 135 MHz at 3.3 V, and by using proprietary Phase Locked Loop (PLL) techniques, produces a divide by 1, 2, 4, or 8 of the input clock. There are two outputs on

文件：59.89 Kbytes 页数：4 Pages

ICST