9-bit to 18-bit HSTL-to-LVTTL memory address latch

文件：70.52 Kbytes 页数：8 Pages

PHI

飞利浦

9-bit to 18-bit HSTL-to-LVTTL memory address latch

恩XP

恩智浦

9-bit to 18-bit HSTL-to-LVTTL memory address latch

文件：70.52 Kbytes 页数：8 Pages

PHI

飞利浦

9-bit to 18-bit HSTL-to-LVTTL memory address latch

OverviewThe HSTL16918 is a 9-bit to 18-bit D-type latch designed for 3.15 to 3.45 V VCC operation. The D inputs accept HSTL levels and the Q outputs provide LVTTL levels.\n The HSTL16918 is particularly suitable for driving an address bus to two banks of memory. Each bank of nine outputs is controll \n\n•Inputs meet JEDEC HSTL Std. JESD 8-6, and outputs meet Level III specifications\n\n•ESD classification testing is done to JEDEC Standard JESD22. Protection exceeds 2000 V to HBM per method A114.\n\n•Latch-up testing is done to JEDEC Standard JESD78, which exceeds 100 mA.\n\n•Packaged in 48-pin ;

恩XP

恩智浦