HSTL16918DGG中文资料9-bit to 18-bit HSTL-to-LVTTL memory address latch数据手册恩XP规格书

描述 Description

OverviewThe HSTL16918 is a 9-bit to 18-bit D-type latch designed for 3.15 to 3.45 V VCC operation. The D inputs accept HSTL levels and the Q outputs provide LVTTL levels.
The HSTL16918 is particularly suitable for driving an address bus to two banks of memory. Each bank of nine outputs is controlled with its own latch-enable (LE) input.
Each of the nine D inputs is tied to the inputs of two D-type latches that provide true data (Q) at the outputs. While LE is LOW the Q outputs of the corresponding nine latches follow the D inputs. When LE is taken HIGH, the Q outputs are latched at the levels set up at the D inputs.
The HSTL16918 is characterized for operation from 0 to +70 Cel.

特性 Features

•Inputs meet JEDEC HSTL Std. JESD 8-6, and outputs meet Level III specifications

•ESD classification testing is done to JEDEC Standard JESD22. Protection exceeds 2000 V to HBM per method A114.

•Latch-up testing is done to JEDEC Standard JESD78, which exceeds 100 mA.

•Packaged in 48-pin plastic thin shrink small outline package (TSSOP48)