HM658512A中文资料日立数据手册PDF规格书

描述 Description

The Hitachi HM658512A is a CMOS pseudo static RAM organized 512-kword × 8-bit. It realizes higher density, higher performance and low power consumption by employing 0.8 µm Hi-CMOS process technology.

特性 Features

• Single 5 V (±10)

• High speed

- Access time CE access time: 70/80/100 ns (max)

- Cycle time Random read/write cycle time: 115/130/160 ns (min)

• Low power

- Active: 250 mW (typ)

- Standby: 200 µW (typ)

• Directly TTL compatible All inputs and outputs

• Simple address configuration Non multiplexed address

• Refresh cycle

- 2048 refresh cycles: 32 ms

• Easy refresh functions Address refresh Automatic refresh Self refresh