HM5225645F中文资料日立数据手册PDF规格书

Description

The Hitachi HM5225645F is a 256-Mbit SDRAM organized as 1048576-word × 64-bit × 4-bank. The Hitachi HM5225325F is a 256-Mbit SDRAM organized as 2097152-word × 32-bit × 4-bank. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 108 bump BGA.

Features

• Single chip wide bit solution (× 64/× 32)

• 3.3 V power supply

• Clock frequency: 100 MHz (max)

• LVTTL interface

• Extremely small foot print: 1.27 mm pitch

- Package: BGA (BP-108)

• 4 banks can operate simultaneously and independently

• Burst read/write operation and burst read/single write operation capability

• Programmable burst length: 4/8/full page

• 2 variations of burst sequence

- Sequential (BL = 4/8/full page)

- Interleave (BL = 4/8)

• Programmable CAS latency: 2/3

• Byte control by DQMB