128M LVTTL interface SDRAM 100 MHz 1-Mword ×32-bit ×4-bank PC/100 SDRAM

Description\nThe Hitachi HM5212325FBPC is a 128-Mbit SDRAM organized as 1048576-word ×32-bit ×4-bank. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 90-bump fine pitch BGA. •  Single chip wide bit solution (×32)\n•  3.3 V power supply\n•  Clock frequency: 100 MHz (max)\n•  LVTTL interface\n•  Extremely small foot print: 0.8 mm pitch \n    Package: FBGA (BP-90)\n•  4 banks can operate simultaneously and independently\n•  Burst read/write operation and burst read/single ;

HITACHI

日立

TSSOP

日立

上传：深圳市勤思达科技有限公司

DIP28

HIT

上传：谛辉(北京/上海/青岛 )电子科技有限公司

DIP-28

HITACHIHitachi Semiconductor

日立日立公司

上传：深圳市恒达亿科技有限公司

DIP-32

HITACHI/日立

上传：深圳市威尔健半导体有限公司