HEF4518BT集成电路（IC）的计数器除法器规格书PDF中文资料

1. General description

The HEF4518B is a dual 4-bit internally synchronous BCD counter. The counter has two clock

inputs (CP0 and CP1 ), buffered outputs from all four bit positions (O0 to O3) and an asynchronous

master reset input (MR). The counter advances on either the LOW to HIGH transition of the CP0

input if CP1 is HIGH or the HIGH to LOW transition of the CP1 input if CP0 is LOW. Either CP0

or CP1 may be used as the clock input to the counter and the other clock input may be used as

a clock enable input. A HIGH on MR resets the counter (O0 to O3 = LOW) independent of CP0

and CP1. Schmitt-trigger action in the clock inputs makes the circuit highly tolerant to slower clock

rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to

interface inputs to voltages in excess of VDD.

2. Features and benefits

• Wide supply voltage range from 3.0 V to 15.0 V

• CMOS low power dissipation

• High noise immunity

• Tolerant of slow clock rise and fall times

• Fully static operation

• 5 V, 10 V, and 15 V parametric ratings

• Standardized symmetrical output characteristics

• Complies with JEDEC standard JESD 13-B

• ESD protection:

• HBM JESD22-A114F exceeds 2000 V

• MM JESD22-A115-A exceeds 200 V

• Specified from -40 °C to +85 °C

3. Applications

• Multistage synchronous counting

• Multistage asynchronous counting

• Frequency dividers