HEF4517BD中文资料飞利浦数据手册PDF规格书

DESCRIPTION

The HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (CP), data input (D), parallel input-enable/output-enable (PE/EO) and four 3-state outputs of the 16th, 32nd, 48th and 64th bit positions (O16 to O64). Data at the D input is entered into the first bit on the LOW to HIGH transition of the clock, regardless of the state of PE/EO.

When PE/EO is LOW the outputs are enabled and the device is in the 64-bit serial mode.

When PE/EO is HIGH the outputs are disabled (high impedance OFF-state), the 64-bit shift register is divided into four 16-bit shift registers with D, O16, O32 and O48 as data inputs of the 1st, 17th, 33rd, and 49th bit respectively. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.