Dual 64-bit static shift register

DESCRIPTION The HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (CP), data input (D), parallel input-enable/output-enable (PE/EO) and four 3-state outputs of the 16th, 32nd, 48th and 64th bit positions (O16 to O64). Data at the D inp

文件：75.76 Kbytes 页数：8 Pages

PHI

PHI

Dual 64-bit static shift register

DESCRIPTION The HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (CP), data input (D), parallel input-enable/output-enable (PE/EO) and four 3-state outputs of the 16th, 32nd, 48th and 64th bit positions (O16 to O64). Data at the D inp

文件：75.76 Kbytes 页数：8 Pages

PHI

PHI

Dual 64-bit static shift register

DESCRIPTION The HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (CP), data input (D), parallel input-enable/output-enable (PE/EO) and four 3-state outputs of the 16th, 32nd, 48th and 64th bit positions (O16 to O64). Data at the D inp

文件：75.76 Kbytes 页数：8 Pages

PHI

PHI

Dual 64-bit static shift register

DESCRIPTION The HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (CP), data input (D), parallel input-enable/output-enable (PE/EO) and four 3-state outputs of the 16th, 32nd, 48th and 64th bit positions (O16 to O64). Data at the D inp

文件：75.76 Kbytes 页数：8 Pages

PHI

PHI