7-stage binary counter

DESCRIPTION The HEF4024B is a 7-stage binary ripple counter with a clock input (CP), and overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (O0 to O6). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and force

文件：42.52 Kbytes 页数：5 Pages

PHI

飞利浦

7-stage binary counter

DESCRIPTION The HEF4024B is a 7-stage binary ripple counter with a clock input (CP), and overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (O0 to O6). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and force

文件：42.52 Kbytes 页数：5 Pages

PHI

飞利浦

7-stage binary counter

DESCRIPTION The HEF4024B is a 7-stage binary ripple counter with a clock input (CP), and overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (O0 to O6). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and force

文件：42.52 Kbytes 页数：5 Pages

PHI

飞利浦

7-stage binary counter

DESCRIPTION The HEF4024B is a 7-stage binary ripple counter with a clock input (CP), and overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (O0 to O6). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and force

文件：42.52 Kbytes 页数：5 Pages

PHI

飞利浦