Single Port Bypass Circuit with CDR & Data Valid Detection Capability for Fibre Channel Arbitrated Loops

Description The HDMP-0422 is a Single Port Bypass Circuit (PBC) with Clock and Data Recovery (CDR) capability included. This integrated circuit provides a low-cost, lowpower physical-layer solution for Fibre Channel Arbitrated Loop (FC-AL) disk array configurations. By using a PBC such as the HDM

文件：242.11 Kbytes 页数：14 Pages

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Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops

Description The HDMP-0440 is a Quad Port Bypass Circuit (PBC), which provides a low-cost, low-power physical-layer solution for Fibre Channel Arbitrated Loop (FC-AL) disk array configurations. By using a PBC such as the HDMP-0440, hard disks may be pulled out or swapped while other disks in the a

文件：271.42 Kbytes 页数：10 Pages

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Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops

Description The HDMP-0450 is a Quad Port Bypass Circuit (PBC) which provides a low-cost, low-power physical-layer solution for Fibre Channel Arbitrated Loop (FC-AL) disk array configurations. By using a PBC such as the HDMP-0450, hard disks may be pulled out or swapped while other disks in the ar

文件：269.5 Kbytes 页数：10 Pages

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Quad Port Bypass Circuit with CDR for Fibre Channel Arbitrated Loops

Description The HDMP-0452 is a Quad Port Bypass Circuit (PBC) with a Clock and Data Recovery (CDR) circuit included. This device minimizes part count, cost and jitter accumulation while repeating incoming signals. Port Bypass Circuits are used in hard disk arrays constructed in Fibre Channel Arbi

文件：273.29 Kbytes 页数：12 Pages

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Octal Cell Port Bypass Circuit without Clock and Data Recovery

Description The HDMP-0480 is an Octal Cell Port Bypass Circuit (PBC). This device minimizes part count, cost and jitter accumulation. Port Bypass Circuits are used in hard disk arrays constructed in Fibre Channel Arbitrated Loop (FC-AL) configurations. By using Port Bypass Circuits, hard disks ma

文件：121.11 Kbytes 页数：11 Pages

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Octal Cell Port Bypass Circuit with CDR and Data Valid Detection

Description The HDMP-0482 is an Octal Cell Port Bypass Circuit (PBC) with Clock and Data Recovery (CDR) and data valid detection capability included. This device minimizes part count, cost and jitter accumulation while repeating incoming signals. Port Bypass Circuits are used in hard disk arrays

文件：149.11 Kbytes 页数：12 Pages

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4Low Cost Gigabit Rate Transmit/Receive Chip Set

Description The HDMP-1012 transmitter and the HDMP-1014 receiver are used to build a high speed data link for point to point communication. The monolithic silicon bipolar transmitter chip and receiver chip are each provided in a standard aluminum M-Quad 80 package. Features • Transparent, Exten

文件：321.18 Kbytes 页数：42 Pages

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4Low Cost Gigabit Rate Transmit/Receive Chip Set

Description The HDMP-1012 transmitter and the HDMP-1014 receiver are used to build a high speed data link for point to point communication. The monolithic silicon bipolar transmitter chip and receiver chip are each provided in a standard aluminum M-Quad 80 package. Features • Transparent, Exten

文件：321.18 Kbytes 页数：42 Pages

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Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os

Description The HDMP-1022 transmitter and the HDMP-1024 receiver are used to build a high-speed data link for point-to-point communication. The monolithic silicon bipolar transmitter chip and receiver chip are each provided in a standard aluminum M-Quad 80 package. Features • Transparent, Exten

文件：321.37 Kbytes 页数：40 Pages

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Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os

Description The HDMP-1022 transmitter and the HDMP-1024 receiver are used to build a high-speed data link for point-to-point communication. The monolithic silicon bipolar transmitter chip and receiver chip are each provided in a standard aluminum M-Quad 80 package. Features • Transparent, Exten

文件：321.37 Kbytes 页数：40 Pages

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