Octal Transparent Latches (with 3-state outputs)

Description When the latch enable (LE) input is high, the Q outputs of HD74HCT563 will follow the inversion of the D inputs and the Q outputs of HD74HCT573 will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns hig

文件：138.1 Kbytes 页数：10 Pages

RENESAS

瑞萨

Octal Transparent Latches (with 3-state outputs)

Description When the latch enable (LE) input is high, the Q outputs of HD74HCT563 will follow the inversion of the D inputs and the Q outputs of HD74HCT573 will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns hig

文件：138.1 Kbytes 页数：10 Pages

RENESAS

瑞萨

Octal 3-State Noninverting Transparent Latch High-Performance Silicon-Gate CMOS

The IN74HCT573A is identical in pinout to the LS/ALS573. This device may be used as a level converter for interfacing TTL or NMOS outputs to High-Speed CMOS inputs. These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes

文件：115.33 Kbytes 页数：5 Pages

INTEGRAL

Integral Corp.

Octal 3-State Noninverting Transparent Latch High-Performance Silicon-Gate CMOS

The IN74HCT573A is identical in pinout to the LS/ALS573. This device may be used as a level converter for interfacing TTL or NMOS outputs to High-Speed CMOS inputs. These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes

文件：237.81 Kbytes 页数：6 Pages

IKSEMICON