3-to-8-line Decoder/Demultiplexer

Description The HD74HCT238 has 3 binary select inputs (A, B, and C). If the device is enabled these inputs determined which one of the eight normally high outputs will go low. Two active low and one active high enables (G1, G2A and G2B) are provided to ease the cascading of decoders. Features •

文件：186.64 Kbytes 页数：6 Pages

RENESAS

瑞萨

3-to-8-line Decoder/Demultiplexer

Description The HD74HCT238 has 3 binary select inputs (A, B, and C). If the device is enabled these inputs determined which one of the eight normally high outputs will go low. Two active low and one active high enables (G1, G2A and G2B) are provided to ease the cascading of decoders. Features •

文件：186.64 Kbytes 页数：6 Pages

RENESAS

瑞萨

3-to-8 line decoder/demultiplexer

GENERAL DESCRIPTION The 74HC/HCT238 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Demultiplexing capability • Multiple input enable for easy expansion • Ideal for mem

文件：49.61 Kbytes 页数：7 Pages

PHI

飞利浦

3-to-8 line decoder/demultiplexer

1. General description The 74HC238; 74HCT238 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1 and E2 and E3). Every output will be LOW unless E1 and E2 are LOW and E3 is HIGH. This multiple e

文件：267.32 Kbytes 页数：15 Pages

NEXPERIA

安世