3-to-8-line Decoder/Demultiplexer with Address Latch

Description The HD74HCT137 implements a three-to-eight line decoder with latches on the three address inputs. When GL goes from low to high, the address present at the select inputs (A, B and C) is stored in the latches. As long as GL remains high no address changes will be recognized. Output ena

文件：197.84 Kbytes 页数：8 Pages

RENESAS

瑞萨

3-to-8-line Decoder/Demultiplexer with Address Latch

Description The HD74HCT137 implements a three-to-eight line decoder with latches on the three address inputs. When GL goes from low to high, the address present at the select inputs (A, B and C) is stored in the latches. As long as GL remains high no address changes will be recognized. Output ena

文件：197.84 Kbytes 页数：8 Pages

RENESAS

瑞萨

3 TO 8 LINE DECODER/LATCH INVERTING

DESCRIPTION TheM54/74HCT137 isahigh speed CMOS3TO8LINE DECODER/LATCH (INVERTING) fabricated in silicon gateC2MOStechnology. Ithas the samehigh speedperformanceofLSTTL combined withtrueCMOSlowpower consumption. ■ HIGH SPEED tPD = 17 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC = 4 µA (MAX

文件：260.839 Kbytes 页数：12 Pages

STMICROELECTRONICS

意法半导体

3-to-8 line decoder/demultiplexer with address latches; inverting

GENERAL DESCRIPTION The 74HC/HCT137 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Combines 3-to-8 decoder with 3-bit latch • Multiple input enable for easy expansion or ind

文件：68.59 Kbytes 页数：8 Pages

PHI

飞利浦

3-to-8 line decoder/demultiplexer with address latches; inverting

文件：72.22 Kbytes 页数：8 Pages

PHI

飞利浦

High Speed CMOS Logic, 3-to-8 Line Decoder Demultiplexer with Address Latches

文件：65.099 Kbytes 页数：10 Pages

TI

德州仪器