HD74HCT137FPEL

3-to-8-line Decoder/Demultiplexer with Address Latch

Description TheHD74HCT137implementsathree-to-eightlinedecoderwithlatchesonthethreeaddressinputs.WhenGLgoesfromlowtohigh,theaddresspresentattheselectinputs(A,BandC)isstoredinthelatches.AslongasGLremainshighnoaddresschangeswillberecognized.Outputena

74HCT137

3-to-8linedecoder/demultiplexerwithaddresslatches;inverting

GENERALDESCRIPTION The74HC/HCT137arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL(LSTTL).TheyarespecifiedincompliancewithJEDECstandardno.7A. FEATURES •Combines3-to-8decoderwith3-bitlatch •Multipleinputenableforeasyexpansionorind

PHI

74HCT137

3-to-8linedecoder/demultiplexerwithaddresslatches;inverting

PHI

CD74HCT137

HighSpeedCMOSLogic,3-to-8LineDecoderDemultiplexerwithAddressLatches

HD74HCT137RPEL

3-to-8-lineDecoder/DemultiplexerwithAddressLatch

Description TheHD74HCT137implementsathree-to-eightlinedecoderwithlatchesonthethreeaddressinputs.WhenGLgoesfromlowtohigh,theaddresspresentattheselectinputs(A,BandC)isstoredinthelatches.AslongasGLremainshighnoaddresschangeswillberecognized.Outputena

M74HCT137

3TO8LINEDECODER/LATCHINVERTING

DESCRIPTION TheM54/74HCT137isahighspeedCMOS3TO8LINEDECODER/LATCH(INVERTING)fabricatedinsilicongateC2MOStechnology.IthasthesamehighspeedperformanceofLSTTLcombinedwithtrueCMOSlowpowerconsumption. ■HIGHSPEEDtPD=17ns(TYP.)ATVCC=5V ■LOWPOWERDISSIPATIONICC=4µA(MAX