Dual J-K Flip-Flops (with Preset and Clear)

Description Each flip-flop has independent J, K, preset, clear, and clock inputs and Q and Q outputs. This device is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Clear and preset are independent of the clock and accomplished by a low lo

文件：99.99 Kbytes 页数：7 Pages

RENESAS

瑞萨

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

DESCRIPTION The M74HC76 is an high speed CMOS DUAL J-K FLIP FLOP WITH CLEAR fabricated with silicon gate C2MOS technology. ■ HIGH SPEED : fMAX = 67MHz (TYP.) at VCC = 6V ■ LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C ■ HIGH NOISE IMMUNITY: VNIH = VNIL = 28 VCC (MIN.) ■ SYMMETRICAL OUTPUT

文件：508.59 Kbytes 页数：11 Pages

STMICROELECTRONICS

意法半导体

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

DESCRIPTION The M54/74HC76 is a high speed CMOSDUAL J-K FLIP FLOP fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. Depending on with the logic level at the J and K inputs this device changes state on the ne

文件：251.87 Kbytes 页数：11 Pages

STMICROELECTRONICS

意法半导体

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

DESCRIPTION The M74HC76 is an high speed CMOS DUAL J-K FLIP FLOP WITH CLEAR fabricated with silicon gate C2MOS technology. ■ HIGH SPEED : fMAX = 67MHz (TYP.) at VCC = 6V ■ LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C ■ HIGH NOISE IMMUNITY: VNIH = VNIL = 28 VCC (MIN.) ■ SYMMETRICAL OUTPUT

文件：508.59 Kbytes 页数：11 Pages

STMICROELECTRONICS

意法半导体