Dual JK Negative Edge-Triggered Flip-Flop

Description The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous Set and Clear inputs to each flip-flop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may change when the clock is High and the bistable will p

文件：59.65 Kbytes 页数：10 Pages

HitachiHitachi Semiconductor

日立日立公司

Dual JK Negative Edge-Triggered Flip-Flop

Description The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous Set and Clear inputs to each flipflop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may change when the clock is High and the bistable will

文件：240.9 Kbytes 页数：10 Pages

RENESAS

瑞萨

Dual JK Negative Edge-Triggered Flip-Flop

HITACHI

日立

DUAL J-K FLIP-FLOP WITH SET AND RESET

DUAL J-K FLIP-FLOP WITH SET AND RESET High-Speed Silicon-Gate CMOS The IN74ACT112 is identical in pinout to the LS/ALS112, HC/HCT112. The IN74ACT112 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. Each flip-flop is negative-edge clocked and has ac

文件：202.46 Kbytes 页数：5 Pages

INTEGRAL

Integral Corp.

Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS

Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS The IN74ACT112 is identical in pinout to the LS/ALS112, HC/HCT112. The IN74ACT112 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. Each flip-flop is negative-edge clocked and has ac

文件：219.36 Kbytes 页数：6 Pages

IKSEMICON

DUAL J-K FLIP-FLOP WITH SET AND RESET

DUAL J-K FLIP-FLOP WITH SET AND RESET High-Speed Silicon-Gate CMOS The IN74ACT112 is identical in pinout to the LS/ALS112, HC/HCT112. The IN74ACT112 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. Each flip-flop is negative-edge clocked and has ac

文件：202.46 Kbytes 页数：5 Pages

INTEGRAL

Integral Corp.