HD74ACT112中文资料瑞萨数据手册PDF规格书

Description

The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous Set and Clear inputs to each flipflop.

When the clock goes High, the inputs are enabled and data will be accepted. The logic level of the J and K inputs

may change when the clock is High and the bistable will perform according to the Truth Table as long as minimum

setup and hold times are observed. Input data is transferred to the outputs on the falling edge of the clock pulse.

Features

• Outputs Source/Sink 24 mA

• HD74ACT112 has TTL-Compatible Inputs

• Ordering Information: Ex. HD74AC112