HCF4724BEY中文资料意法半导体数据手册PDF规格书

DESCRIPTION

The HCC/HCF4724B 8-bit addressable latch is a serial-input, parallel-output storage register that can perform a variety of functions.

■ SERIAL DATA INPUT - ACTIVE PARALLEL OUTPUT

■ STORAGE REGISTER CAPABILITY - MASTER CLEAR

■ CAN FUNCTION AS DEMULTIPLEXER

■ STANDARDIZED, SYMMETRICAL OUTPUT CHARACTER

■ 100 TESTED FOR QUIESCENT CURRENT AT 20V

■ MAXIMUM INPUT CURRENT OF 1µA AT 18V (full package-temperature range), 100nA AT 18V AND 25oC

■ NOISE MARGIN (full package-temperature range) = 1V AT VDD =5V, 2V AT VDD = 10V, 2.5V AT VDD = 15V

■ 5V, 10V, AND 15V PARAMETRIC RATINGS

■ MEETS ALL REQUIREMENTS OF JEDECTENTATIVE STANDARD N. 13A, ” STANDARD SPECIFICATIONS FOR DESCRIPTION OF ’ B ’ SERIES CMOS DEVICES ”

APPLICATION

■ MULTI-LINE DECODERS

■ A/D CONVERTERS