H5TQ2G63FFR中文资料DDR3 SDRAM数据手册SK hynix规格书

描述 Description

The H5TQ2G8(6)3FFR-xxI and H5TQ2G8(6)3FFR-xxK are a 2,147,483,648-bit CMOS Double DataRate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. SK Hynix 2Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it.
The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth

特性 Features

• VDD=VDDQ=1.5V +/- 0.075V 
• Fully differential clock inputs (CK, /CK) operation 
• Differential Data Strobe (DQS, /DQS) 
• On chip DLL align DQ, DQS and /DQS transition with CK transition 
• DM masks write data-in at the both rising and falling edges of the data strobe 
• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock 
• Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 13 and 14 supported 
• Programmable additive latency 0, CL-1, and CL-2 supported 
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9
• Programmable burst length 4/8 with both nibble sequential and interleave mode 
• BL switch on the fly 
• 8banks 
• Average Refresh Cycle(Tcase of 0oC~ 95oC)- 7.8 μs at 0oC ~ 85oC- 3.9 μs at 85oC ~ 95oC - 1.95 μs at 95oC ~ 105oCAutomotive IT Temperature( -40oC ~ 95oC)Automotive AT Temperature( -40oC ~ 105 oC)  
• JEDEC standard 78ball FBGA(x8), 96ball FBGA (x16) 
• Driver strength selected by EMRS 
• Dynamic On Die Termination supported 
• Asynchronous RESET pin supported 
• ZQ calibration supported 
• TDQS (Termination Data Strobe) supported (x8 only) 
• Write Levelization supported 
• 8 bit pre-fetch