H2A402G1666B中文资料2Gb (16Mx8Banksx16) DDR3 SDRAM数据手册Axeme规格书

描述 Description

The H2A402G1666B is a high speed Double Date Rate 3 (DDR3) low voltage Synchronous DRAM fabricated with ultra high performance CMOS process containing 2,147,483,648 bits which organized as 16Mbits x 8 banks by 16 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin (DDR3-1600) for general applications. The chip is designed to comply with the following key DDR3 SDRAM features:
posted CAS with additive latency,write latency = read latency -1,On Die Termination,programmable driver strength data,seamless BL4 access with bank-grouping.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style. The 2Gb DDR3 devices operates with a single power supply: 1.5V±0.075V VDD and VDDQ.
Available package: FBGA-96Ball (with 0.8mm x 0.8mm ball pitch)

特性 Features

• All inputs and outputs are compatible with SSTL_15 interface.
• Eight Banks
• Bust length: 4 with Burst Chop (BC) and 8.
• CAS Latency (CL): 9, 10, 11
• Bi-directional Differential Data Strobe (DQS).
• Data outputs on DQS, /DQS edges when read.
• DM mask write data-in at the both rising and falling edges of the data strobe.
• Multi Purpose Register (MPR) for pre-defined pattern read out
• Auto Refresh and Self Refresh
• Refresh Interval: 7.8us Tcase between-40°C ~ 85°C
• RoHS Compliance
• High Temperature Self-Refresh rate enable
• RESET pin for initialization and reset function