GTL16616数据手册TI中文资料规格书

描述 Description

DESCRIPTION/ORDERING INFORMATION
The SN74GTL16616 is a 17-bit UBT™ transceiver that provides LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL signal-level translation. Combined D-type flip-flops and D-type latches allow for transparent, latched, clocked, and clocked-enabled modes of data transfer identical to the 16601 function. Additionally, this device provides for a copy of CLKAB at GTL/GTL+ signal levels (CLKOUT) and conversion of a GTL/GTL+ clock to LVTTL logic levels (CLKIN). This device provides an interface between cards operating at LVTTL logic levels and a backplane operating at GTL/GTL+ signal levels. Higher-speed operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels, and OEC™ circuitry.FEATURES
• Member of the Texas Instruments Widebus™ Family
• UBT™ Transceiver Combines D-Type Latches
   and D-Type Flip-Flops for Operation in
   Transparent, Latched, Clocked, or
   Clock-Enabled Modes
• OEC™ Circuitry Improves Signal Integrity and
   Reduces Electromagnetic Interference
• GTL Buffered CLKAB Signal (CLKOUT)
• Translates Between GTL/GTL+ Signal Levels
   and LVTTL Logic Levels
• Supports Mixed-Mode (3.3 V and 5 V) Signal
   Operation on A-Port and Control Inputs
• Equivalent to 16601 Function
• Ioff Supports Partial-Power-Down Mode Operation
• Bus Hold on Data Inputs Eliminates the Need
   for External Pullup/Pulldown Resistors on
   A Port
• Distributed VCC and GND Pins Minimize
   High-Speed Switching Noise
• Latch-Up Performance Exceeds 100 mA Per
   JESD 78, Class II
• ESD Protection Exceeds JESD 22
   – 2000-V Human-Body Model (A114-A)

特性 Features

• Member of the Texas Instruments Widebus™ Family
• UBT™ Transceiver Combines D-Type Latches
   and D-Type Flip-Flops for Operation in
   Transparent, Latched, Clocked, or
   Clock-Enabled Modes
• OEC™ Circuitry Improves Signal Integrity and
   Reduces Electromagnetic Interference
• GTL Buffered CLKAB Signal (CLKOUT)
• Translates Between GTL/GTL+ Signal Levels
   and LVTTL Logic Levels
• Supports Mixed-Mode (3.3 V and 5 V) Signal
   Operation on A-Port and Control Inputs
• Equivalent to 16601 Function
• Ioff Supports Partial-Power-Down Mode Operation
• Bus Hold on Data Inputs Eliminates the Need
   for External Pullup/Pulldown Resistors on
   A Port
• Distributed VCC and GND Pins Minimize
   High-Speed Switching Noise
• Latch-Up Performance Exceeds 100 mA Per
   JESD 78, Class II
• ESD Protection Exceeds JESD 22
   – 2000-V Human-Body Model (A114-A)