GL852F数据手册Genesys中文资料规格书

描述 Description

GL852F is Genesys Logic’s USB general purpose compound solution which fully complies with Universal Serial Bus Specification Revision 2.0. It features 4 downstream ports and has one more internal downstream port connected to general purpose device. GL852F provides up to 17 General Purpose I/O (GPIO) pins to support general purpose and other applications. The MTT architecture provides every downstream port with individual traffic control for the best performance when connected with several Full/Low-Speed devices and running heavy bandwidth-consuming operations concurrently.\r
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GL852F embeds an 8-bit 8052-like microcontroller with 16 K-bytes built-in SRAM for firmware customization features. The internal SRAM memory space supports multiple programming of applications firmware through USB upstream port, providing higher design flexibility comparing to traditional mask-ROM architecture. \r
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GL852F’s design architecture provides multiple advantages on minimizing the cost of system Built-of-Material (BOM). For example, the hardware featured built-in 5 to 3.3V power regulator, on-chip power on reset, and internal Phase Lock Loop (PLL) that provide multiple clock sources with single 12MHz external crystal. In addition, OEM vendor’s configuration setting and PID/VID can be customized and stored in the internal memory to eliminate the need of using external EEPROM. \r
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*TT (transaction translator) is the main traffic control engine in an USB 2.0 hub to handle the unbalanced traffic speed between the upstream port and the downstream ports.

特性 Features

General Features\r
• Compliant to USB specification 2.0\r
• On-chip 8-bit micro-processor\r
– Operation speed: 12MHz clock input\r
– 8052-like architecture\r
– USB optimized instruction set\r
– C compiler support\r
– 16 K-Byte embedded SRAM for multiple firmware programming \r
– max frequency 30Mhz\r
– 256 byte of RAM for basic operation\r
• Integrated ultra low power USB transceiver\r
• Support both individual and gang modes of power management for each downstream ports\r
• Built-in upstream 1.5KΩ pull-up and downstream 15KΩ pull-down\r
• Configurable compound-device support\r
• On-chip 3.3V output provided by integrated 5-to-3.3V power regulator\r
• On-chip Phase Clock Loop (PLL) providing multiple clock source with single 12 MHz clock input\r
• Improved output drivers with slew-rate control for EMI reduction\r
• Internal power-fail detection for ESD recovery (watch dog timer)\r
• 64 pin (7x7mm) LQFP and 48 pin (7x7mm) LQFP lead-free, RoHS compliant package\r
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USB Hub Features\r
• On-chip power-on reset (POR) USB hub Features\r
– 4 downstream ports that fully compliant to USB specification Revision 2.0\r
– Multiple Transaction Translator (MTT) architecture that enhance performance\r
– Upstream port supports both high speed (HS) and full speed (FS) traffic\r
– Downstream ports support HS, FS, and low speed(LS) traffic\r
– Support 1 device address for hub, 1 device address for general purpose\r
♦ 1 control pipe(endpoint 0: 64-byte data payload) and 1 interrupt pipe(endpoint 1: 1-byte data payload)\r
♦ 1 control pipe(endpoint 0: 64-byte data payload) and 3 interrupt pipe(endpoint 2: 64-byte data payload; endpoint 3, 4: 8-byte data payload)\r
– backward compatible to USB specification Revision 1.1\r
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USB General Purpose Device Features\r
• Conforms to USB HID Class Specification, Revision 1.1\r
• I/O ports\r
– Up to 17 pins for general purpose I/O pin (LQFP64 package)\r
– Remote wakeup capability \r
– up to 6 pins can remote wakeup\r
– Unused I/O pins can be configured as status LED (see Ch3 pin descriptions for detail)