GAL16LV8C-10LJ数据手册集成电路（IC）的CPLD（复杂可编程逻辑器件）规格书PDF

描述 Description

The GAL16LV8D, at 3.5 ns maximum propagation delay time, provides the highest speed performance available in the PLD market. The GAL16LV8C can interface with both 3.3V and 5V signal levels. The GAL16LV8 is manufactured using Lattice Semiconductor's advanced 3.3V E2CMOS process, which combines CMOS with Electrically Erasable (E2) floating gate technology. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently.

特性 Features

• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
   — 3.5 ns Maximum Propagation Delay
   — Fmax = 250 MHz
   — 2.5 ns Maximum from Clock Input to Data Output
   — UltraMOS® Advanced CMOS Technology
• 3.3V LOW VOLTAGE 16V8 ARCHITECTURE
   — JEDEC-Compatible 3.3V Interface Standard
   — 5V Compatible Inputs
   — I/O Interfaces with Standard 5V TTL Devices (GAL16LV8C)
• ACTIVE PULL-UPS ON ALL PINS (GAL16LV8D Only)
• E2 CELL TECHNOLOGY
   — Reconfigurable Logic
   — Reprogrammable Cells
   — 100% Tested/100% Yields
   — High Speed Electrical Erasure (<100ms)
   — 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
   — Maximum Flexibility for Complex Logic Designs
   — Programmable Output Polarity
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
   — 100% Functional Testability
• APPLICATIONS INCLUDE:
   — Glue Logic for 3.3V Systems
   — DMA Control
   — State Machine Control
   — High Speed Graphics Processing
   — Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
• LEAD-FREE PACKAGE OPTIONS