Low Voltage E2CMOS PLD Generic Array Logic

文件：338.08 Kbytes 页数：22 Pages

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Low Voltage E2CMOS PLD Generic Array Logic?

文件：282.63 Kbytes 页数：22 Pages

Lattice

莱迪思

Low Voltage E2CMOS PLD Generic Array Logic?

文件：282.63 Kbytes 页数：22 Pages

Lattice

莱迪思

Low Voltage E2CMOS PLD eneric Array Logic™

Description\nThe GAL16LV8D, at 3.5 ns maximum propagation delay time, provides the highest speed performance available in the PLD market. The GAL16LV8C can interface with both 3.3V and 5V signal levels. The GAL16LV8 is manufactured using Lattice Semiconductor's advanced 3.3V E2CMOS process, which co • HIGH PERFORMANCE E2CMOS® TECHNOLOGY\n   — 3.5 ns Maximum Propagation Delay\n   — Fmax = 250 MHz\n   — 2.5 ns Maximum from Clock Input to Data Output\n   — UltraMOS® Advanced CMOS Technology\n• 3.3V LOW VOLTAGE 16V8 ARCHITECTURE\n   — JEDEC-Compatible 3.3V Interface Standard\n   — 5V Compatible Inp;

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Package：20-LCC（J 形引线）；包装：托盘 类别：集成电路（IC） CPLD（复杂可编程逻辑器件） 描述：IC CPLD 8MC 10NS 20PLCC

Lattice Semiconductor Corporation