5V LVDS 4-Bit High Speed Differential Receiver

General Description This quad receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels. LVDS provides low EMI at ultra low po

文件：246.04 Kbytes 页数：6 Pages

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仙童半导体

5V LVDS 4-Bit High Speed Differential Receiver

General Description This quad receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels. LVDS provides low EMI at ultra low po

文件：249.7 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体

5V LVDS 4-Bit High Speed Differential Receiver

General Description This quad receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels. LVDS provides low EMI at ultra low po

文件：249.7 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体

5V LVDS 4-Bit High Speed Differential Receiver

ONSEMI

安森美半导体

5V LVDS 4-Bit High Speed Differential Receiver

General Description This quad receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels. LVDS provides low EMI at ultra low po

文件：246.04 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体

5V LVDS 4-Bit High Speed Differential Receiver

General Description This quad receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels. LVDS provides low EMI at ultra low po

文件：249.7 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体

5V LVDS 4-Bit High Speed Differential Receiver

General Description This quad receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels. LVDS provides low EMI at ultra low po

文件：246.04 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体

5V LVDS 4-Bit High Speed Differential Receiver

General Description This quad receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels. LVDS provides low EMI at ultra low po

文件：249.7 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体

5V LVDS 4-Bit High Speed Differential Receiver

General Description This quad receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels. LVDS provides low EMI at ultra low po

文件：249.7 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体

5V LVDS 4-Bit High Speed Differential Receiver

General Description This quad receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels. LVDS provides low EMI at ultra low po

文件：249.7 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体