FDC634中文资料仙童半导体数据手册PDF规格书

General Description

These P-Channel logic level enhancement mode power field effect transistors are produced using Fairchilds proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as cellular phone and notebook computer power management and other battery powered circuits where high-side switching, and low in-line power loss are needed in a very small outline surface mount package.

特性 Features

■ -3.5 A, -20 V. RDS(ON) = 0.080 Ω @ VGS = -4.5 V RDS(ON) = 0.110 Ω @ VGS = -2.5 V.

■ SuperSOTTM-6 package design using copper lead frame for superior thermal and electrical capabilities.

■ High density cell design for extremely low RDS(ON).

■ Exceptional on-resistance and maximum DC current capability.