24-Bit, 2 MSPS/500 kSPS, SAR ADCs

GENERAL DESCRIPTION The AD4030-24/AD4032-24 are 2 MSPS or 500 kSPS successive approximation register (SAR), analog-to-digital converters (ADC) with Easy Drive™. With a guaranteed maximum ±0.9 ppm integral nonlinearity (INL) and no missing codes at 24-bits, the AD4030-24/ AD4032-24 achieve unp

文件：2.41379 Mbytes 页数：50 Pages

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Compact, Low Power, 12-Bit, 2 MSPS/500 kSPS Easy Drive SAR ADC

FEATURES ► Small footprint, big performance ► INL: ±0.1 LSB maximum ► SNR: 73.8 dB with VREF = 3.3 V ► 1.35 nJ per conversion ► 1.35 mW/0.68 mW at 1 MSPS/500 kSPS in sample mode ► 370 μW/112 μW at 1 MSPS/300 kSPS in autonomous modes ► 4.1 μW standby power ► Versatile signal conditioning in

文件：2.69201 Mbytes 页数：65 Pages

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Evaluating the AD4080 20-Bit, 40 MSPS, Differential SAR ADC

FEATURES ► Full featured evaluation board for the AD4080 ► Analysis | Control | Evaluation (ACE) Software plug-in available for device configuration, data capture, and performance evaluation ► Flexible analog front end ► On-board power solution and precision reference ► On-board clock gener

文件：3.41345 Mbytes 页数：22 Pages

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20-Bit, 40 MSPS, Differential SAR ADC

GENERAL DESCRIPTION The AD4080 is a high-speed, low noise, low distortion, 20-bit, Easy Drive, successive approximation register (SAR) analog-to-digital converter (ADC). Maintaining high performance (signal-to-noise and distortion (SINAD) ratio > 90 dBFS) at signal frequencies in excess of 1

文件：3.63552 Mbytes 页数：95 Pages

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32 μA, Ultra-Low Power, 16-Bit Sigma-Delta ADC with Integrated PGA and FIFO

FEATURES ► Ultra-low current consumption (typical) ► 32 μA: continuous conversion mode (gain = 128) ► 5 μA: duty cycling mode (ratio = 1/16) ► 0.5 μA: standby mode ► 0.1 μA: power-down mode ► Built-in features for system level power savings ► Current saving duty cycle ratio: 1/4 or 1/16 ►

文件：3.7831 Mbytes 页数：107 Pages

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32 μA, Ultra Low Power, 16-Bit Sigma-Delta ADC with Integrated PGA and FIFO

FEATURES ► Ultra-low current consumption (typical): ► 32 μA: continuous conversion mode (gain = 128) ► 5 μA: duty cycling mode (ratio = 1/16) ► 0.5 μA: standby mode ► 0.1 μA: power-down mode ► Built-in features for system level power savings: ► Current saving duty cycle ratio: 1/4 or 1/16

文件：3.48095 Mbytes 页数：105 Pages

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32 μA, Ultra-Low Power, 24-Bit Sigma-Delta ADC with Integrated PGA and FIFO

FEATURES ► Ultra-low current consumption (typical) ► 32 μA: continuous conversion mode (gain = 128) ► 5 μA: duty cycling mode (ratio = 1/16) ► 0.5 μA: standby mode ► 0.1 μA: power-down mode ► Built-in features for system level power savings ► Current saving duty cycle ratio: 1/4 or 1/16 ►

文件：3.89737 Mbytes 页数：106 Pages

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32 關A, Ultra Low Power, 24-Bit Sigma-Delta ADC with Integrated PGA and FIFO

GENERAL DESCRIPTION The AD4130-8 is an ultra low power, high precision, measurement solution for low bandwidth battery operated applications. The fully integrated analog front end (AFE) includes a multiplexer for up to 16 single-ended or eight differential inputs, programmable gain amplifier

文件：3.54414 Mbytes 页数：108 Pages

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32 μA, Ultra Low Power, 16-Bit Sigma-Delta ADC with Integrated PGA

FEATURES ► Ultra-low current consumption (typical): ► 32 μA: continuous conversion mode (gain = 128) ► 5 μA: duty cycling mode (ratio = 1/16) ► 0.5 μA: standby mode ► 0.1 μA: power-down mode ► Built-in features for system level power savings: ► Current saving duty cycle ratio: 1/4 or 1/16

文件：3.24212 Mbytes 页数：94 Pages

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32 μA, Ultra-Low Power, 16-Bit Sigma-Delta ADC with Integrated PGA

FEATURES ► Ultra-low current consumption (typical) ► 32 μA: continuous conversion mode (gain = 128) ► 5 μA: duty cycling mode (ratio = 1/16) ► 0.5 μA: standby mode ► 0.1 μA: power-down mode ► Built-in features for system level power savings ► Current saving duty cycle ratio: 1/4 or 1/16 ►

文件：3.14233 Mbytes 页数：94 Pages

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