PCI integrated LAN V.90/V.92 modem

ESS

Dual 10-bit bus interface latch 3-State

DESCRIPTION The MB2841 Bus interface register is designed to provide extra data width for wider data/address paths of buses carrying parity. The MB2841 consists of two sets of ten D-type latches with 3-State outputs. The flip-flops appear transparent to the data when Latch Enable (nLE) is High.

文件：66.1 Kbytes 页数：10 Pages

PHI

PHI

Dual 10-bit bus interface latch 3-State

DESCRIPTION The MB2841 Bus interface register is designed to provide extra data width for wider data/address paths of buses carrying parity. The MB2841 consists of two sets of ten D-type latches with 3-State outputs. The flip-flops appear transparent to the data when Latch Enable (nLE) is High.

文件：66.1 Kbytes 页数：10 Pages

PHI

PHI

Programmable, Off-Line, PWM Controller

文件：923.48 Kbytes 页数：9 Pages

TI

德州仪器