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EPM7512AEQC208-7N规格书详情
General Description
MAX 7000A (including MAX 7000AE) devices are high-density, highperformance devices based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROMbased MAX 7000A devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 7000A devices in the -4, -5, -6, -7, and some -10 speed grades are compatible with the timing requirements for 33 MHz operation of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 2.
Features...
■ High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX®) architecture (see Table 1)
■ 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability
– MAX 7000AE device in-system programmability (ISP) circuitry compliant with IEEE Std. 1532
– EPM7128A and EPM7256A device ISP circuitry compatible with IEEE Std. 1532
■ Built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1
■ Supports JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71
■ Enhanced ISP features
– Enhanced ISP algorithm for faster programming (excluding EPM7128A and EPM7256A devices)
– ISP_Done bit to ensure complete programming (excluding EPM7128A and EPM7256A devices)
– Pull-up resistor on I/O pins during in-system programming
■ Pin-compatible with the popular 5.0-V MAX 7000S devices
■ High-density PLDs ranging from 600 to 10,000 usable gates
■ Extended temperature range
■ 4.5-ns pin-to-pin logic delays with counter frequencies of up to
227.3 MHz
■ MultiVoltTM I/O interface enables device core to run at 3.3 V, while I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels
■ Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), ball-grid array (BGA), spacesaving FineLine BGATM, and plastic J-lead chip carrier (PLCC) packages
■ Supports hot-socketing in MAX 7000AE devices
■ Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance
■ PCI-compatible
■ Bus-friendly architecture, including programmable slew-rate control
■ Open-drain output option
■ Programmable macrocell registers with individual clear, preset, clock, and clock enable controls
■ Programmable power-up states for macrocell registers in MAX 7000AE devices
■ Programmable power-saving mode for 50 or greater power reduction in each macrocell
■ Configurable expander product-term distribution, allowing up to 32 product terms per macrocell
■ Programmable security bit for protection of proprietary designs
■ 6 to 10 pin- or logic-driven output enable signals
■ Two global clock signals with optional inversion
■ Enhanced interconnect resources for improved routability
■ Fast input setup times provided by a dedicated path from I/O pin to macrocell registers
■ Programmable output slew-rate control
■ Programmable ground pins
产品属性
- 产品编号:
EPM7512AEQC208-7N
- 制造商:
Intel
- 类别:
集成电路(IC) > CPLD(复杂可编程逻辑器件)
- 系列:
MAX® 7000A
- 包装:
托盘
- 可编程类型:
系统内可编程
- 供电电压 - 内部:
3V ~ 3.6V
- 工作温度:
0°C ~ 70°C(TA)
- 安装类型:
表面贴装型
- 封装/外壳:
208-BFQFP
- 供应商器件封装:
208-PQFP(28x28)
- 描述:
IC CPLD 512MC 7.5NS 208QFP
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
ALTERA |
21+ |
QFP208 |
2000 |
全新原装 鄙视假货15118075546 |
询价 | ||
ALTERA |
11+ |
原厂标准 |
5500 |
ALTERA主营只做进口全新原装公司现货 |
询价 | ||
ALTERA |
2021+ |
QFP |
8630 |
主营《XILINX》《ALTERA》品牌 |
询价 | ||
Altera |
23+ |
208-BFQFP |
11200 |
主营:汽车电子,停产物料,军工IC |
询价 | ||
ALTERA |
23+ |
QFP |
3000 |
全新原装、诚信经营、公司现货销售 |
询价 | ||
ALTERA |
23+ |
QFP |
4865 |
中国航天工业部战略合作伙伴行业领导者 |
询价 | ||
ALTERA(阿尔特拉) |
23+ |
标准封装 |
21663 |
我们只是原厂的搬运工 |
询价 | ||
ALTERA |
1904+ |
QFP208 |
3000 |
自家现货!原装特价供货!一片起卖! |
询价 | ||
ALTERA |
22+ |
QFP |
1450 |
强势库存!绝对原装公司现货! |
询价 | ||
ALTERA |
23+24 |
QFP-208 |
8484 |
ALTERA专营可编程逻辑器件100%原装正品 |
询价 |