Universal Platform System-on-chip Processor

OVERVIEW The EP9312 is an ARM920T-based system-on-a-chip design with a large peripheral set targeted to a variety of applications: • Thin client computers for business and home • Internet radio • Internet access devices • Industrial computers • Specialized terminals • Point of sale terminal

文件：884.7 Kbytes 页数：62 Pages

CIRRUS

凌云逻辑

Universal Platform System-on-chip Processor

OVERVIEW The EP9312 is an ARM920T-based system-on-a-chip design with a large peripheral set targeted to a variety of applications: • Thin client computers for business and home • Internet radio • Internet access devices • Industrial computers • Specialized terminals • Point of sale terminal

文件：884.7 Kbytes 页数：62 Pages

CIRRUS

凌云逻辑

Universal Platform System-on-chip Processor

OVERVIEW The EP9312 is an ARM920T-based system-on-a-chip design with a large peripheral set targeted to a variety of applications: • Thin client computers for business and home • Internet radio • Internet access devices • Industrial computers • Specialized terminals • Point of sale terminal

文件：884.7 Kbytes 页数：62 Pages

CIRRUS

凌云逻辑

Universal Platform System-on-chip Processor

OVERVIEW The EP9312 is an ARM920T-based system-on-a-chip design with a large peripheral set targeted to a variety of applications: • Thin client computers for business and home • Internet radio • Internet access devices • Industrial computers • Specialized terminals • Point of sale terminal

文件：884.7 Kbytes 页数：62 Pages

CIRRUS

凌云逻辑

Universal Platform System-on-chip Processor

OVERVIEW The EP9312 is an ARM920T-based system-on-a-chip design with a large peripheral set targeted to a variety of applications: • Thin client computers for business and home • Internet radio • Internet access devices • Industrial computers • Specialized terminals • Point of sale terminal

文件：884.7 Kbytes 页数：62 Pages

CIRRUS

凌云逻辑

14 Pin DIP 5 Tap Low-Profile TTL Compatible Active Delay Lines

14 Pin DIP 5 Tap Low-Profile TTL Compatible Active Delay Lines Whichever is greater. Delay times referenced from input to leading edges at 25°C, 5.0V, with no load

文件：43.7 Kbytes 页数：1 Pages

PCA

14 Pin DIP 5 Tap Low-Profile TTL Compatible Active Delay Lines

14 Pin DIP 5 Tap Low-Profile TTL Compatible Active Delay Lines Whichever is greater. Delay times referenced from input to leading edges at 25°C, 5.0V, with no load

文件：43.7 Kbytes 页数：1 Pages

PCA

14 Pin DIP 5 Tap Low-Profile TTL Compatible Active Delay Lines

14 Pin DIP 5 Tap Low-Profile TTL Compatible Active Delay Lines Whichever is greater. Delay times referenced from input to leading edges at 25°C, 5.0V, with no load

文件：43.7 Kbytes 页数：1 Pages

PCA

14 Pin DIP 5 Tap Low-Profile TTL Compatible Active Delay Lines

14 Pin DIP 5 Tap Low-Profile TTL Compatible Active Delay Lines Whichever is greater. Delay times referenced from input to leading edges at 25°C, 5.0V, with no load

文件：43.7 Kbytes 页数：1 Pages

PCA

14 Pin DIP 5 Tap Low-Profile TTL Compatible Active Delay Lines

14 Pin DIP 5 Tap Low-Profile TTL Compatible Active Delay Lines Whichever is greater. Delay times referenced from input to leading edges at 25°C, 5.0V, with no load

文件：43.7 Kbytes 页数：1 Pages

PCA