SMD 28 Pin Passive Delay Lines

SMD 28 Pin Passive Delay Lines

文件：30.36 Kbytes 页数：1 Pages

PCA

VIDEO GENLOCK PLL

文件：309.32 Kbytes 页数：9 Pages

IDT

VIDEO GENLOCK PLL

Features • Phase-detector/VCO circuit block • Ideal for genlock system • Reference clock range 12 kHz to 1 MHz for full output clock range • Output clock range of 1.25 to 75 MHz (-01), and 0.625 to 37.5 MHz (-15). See “Allowable Input Frequency to Output Frequency” table for conditions • O

文件：361.5 Kbytes 页数：10 Pages

RENESAS

瑞萨

VIDEO GENLOCK PLL

Description The IDT9173B provide the analog PLL circuit blocks to implement a frequency multiplier. Because the device is configured to use an external divider in the PLL clock feedback path, a large divider can be used to result in a large frequency multiplication ratio. This is useful when usin

文件：310.32 Kbytes 页数：9 Pages

IDT